1. Field of the Invention
The present invention relates to a liquid crystal display provided with an active matrix circuit substrate, which is applicable for high-definition television sets, electronic viewfinders for use in a combination camera/VTR system, head mount displays, projection television sets, and the like. The invention also relates to a method of manufacturing the above-described liquid crystal display.
2. Description of the Related Art
Hitherto, many studies have been made of active matrix liquid crystal displays for use in flat panel displays or projection television sets, resulting in some devices which have been commercially available. Such liquid crystal displays utilize a substrate with high density switching devices in a two-dimensional matrix. One example of such a conventional active matrix liquid crystal display is schematically shown in FIG. 11.
Referring to FIG. 11, the liquid crystal display includes transistor pixel switches 801, a buffer 802, a horizontal shift register 803, and a vertical shift register 804. Television luminance signals and sound signals are compressed into a desired frequency band, and the compressed signals are then sent to the buffer 802. The buffer 802 is driven to follow the frequencies by the horizontal shift register 803.
The signals sent to buffer 802 are transferred to pixel electrodes connected to the transistor drains while the pixel switches 801 remain in the on state by the vertical shift register 804.
Features required for circuits that constitute this panel when the above-described panel is used for a high-definition television set (HDTV) will now be considered. Television signals are transferred to the buffer at a frequency of approximately 45 MHz under the conditions that a frame frequency is 60 Hz; the number of scanning lines is approximately 1000; a horizontal scanning period is approximately 30 .mu.sec (effective scanning period is 27 .mu.sec); and the number of horizontal pixels is approximately 1500. The period required for signal transfer per scanning line ranges from 1 to 2 .mu.sec. In consideration of the above, the following four features are required for each circuit:
(1) Possessing a driving power of 45 MHz or higher of the horizontal shift register; PA1 (2) Possessing a driving power of 500 kHz or higher of the vertical shift register; PA1 (3) Possessing a driving power of 45 MHz or higher of a transfer switch that is driven by the horizontal shift register and is used for transferring television signals to the buffer; and PA1 (4) Possessing a driving power of 500 kHz or higher by a pixel switch.
The driving power referred above is a signal transfer capability determined as follows. When a certain gradation number N is transmitted to liquid crystal pixels, the signal transfer capability should not be larger than (Vm-Vt)/N[V] during the previously-described period per scanning line with respect to all the pixels scanned by the scanning line, wherein Vm indicates a voltage that will provide maximum or minimum transmittance of the liquid crystal; and Vt designates a threshold voltage of the liquid crystal obtained from a V-T (voltage-transmittance) curve.
The above four features illustrate that the driving powers of the pixel switches and the vertical shift register may be small, while high-speed driving powers are required for the horizontal shift register and the buffer. Accordingly, in typical liquid crystal displays, the pixel switches and the vertical shift register are constructed in a monolithic structure of non-single crystal thin film transistors (TFTs) formed of polycrystal silicon, amorphous silicon or the like, while peripheral circuits are formed of IC chips mounted on the exterior.
Attempts have been made to construct the peripheral circuit in the form of a monolithic structure with the pixel switches and the vertical shift register. However, this requires that complicated modifications, such as increasing the size of the transistors, should be made to the circuit, since the driving powers of the individual TFTs are very small.
Meanwhile, attention is being focused on TFTs as a component used for a three-dimensional integrated circuit, a contact sensor or the like, formed in a single crystal silicon layer disposed on an insulating substrate (SOI). The TFTs formed into the SOI substrate have superior characteristics, such as a smaller parasitic capacity, better dielectric separation for preventing the latch-up state, and higher resistance to radiation, in comparison with transistors formed on a conventional single crystal silicon wafer. Based on this fact, many studies are being made of such TFTs based on the assumption that the thickness of a single crystal silicon layer is sufficiently reduced (formed into a super thin film), and transistors are formed in the thin layer. This arrangement may improve characteristics of the transistors, such as higher carrier mobility, better sub-threshold characteristics and the like by virtue of the mechanism inherent in the transistors.
However, super thin-film transistors encounter problems in that there is a sharp deterioration in the drain's resistance to voltages when the gate voltage Vg is zero [V] (in the off state) in accordance with the reduced film thickness. This problem seriously hampers the further development of transistors for applications, which are required to resist higher voltages, such as contact sensors, plane displays and the like.
This problem arises from a floating structure inherent in an insulating substrate having a single crystal silicon layer. This will be explained in greater detail with reference to an N-channel MOSTFT by way of example.
When a bias is applied between the gate and the drain of the transistor, lines of electric force extend in a range from an end of a gate electrode to an end of a drain electrode. Simultaneously, a region having a very high density of an electric field is formed in a drain-channel junction. This electric field particularly concentrates on the interface between the above-mentioned junction and the gate insulating film. Electrons that have been supplied from the source region and have reached the end of the drain are further accelerated by this electric field so as to cause impact ionization in a depletion layer at the drain-channel junction, thus generating holes.
These holes move to the end of the source and are removed from the source electrode. However, as a large amount of holes are generated, they are not removed from the source region and, instead, accumulate in the channel region. As a result, the accumulated holes disadvantageously lower the potential of the channel, which further causes the supply of a larger amount of electrons to the end of the drain. The electrons supplied to the drain once again bring about impact ionization, thus causing additional accumulation of holes in the channel.
In this manner, a positive feedback is provided for a series of operations, such as the concentration of an electric field, the generation of impact ionization and the accumulation of holes. During this process, when the transistor is in the off state, electrons that cause impact ionization are supplied by the generation of a reverse-biased current at the drain-channel junction.
P-channel MOSFETs have substantially the same problem as the N-channel MOSFETs discussed above, although in the former the majority carrier is holes, which have a lower impact ionization rate than that of electrons, such that a smaller adverse influence is produced.
One possible solution to this problem is to quickly remove carriers (holes for N-channel MOSFETs, and electrons for P-channel MOSFETs) from the channel before they accumulate. One method to achieve this is to maintain the potential of the channel (hereinafter referred to as the "SUB potential") at a given potential level, as viewed in the normal IC structure.
However, this method necessitates a region used for extracting the SUB potential, thus increasing the area of the device. This hampers the integration of devices, and further causes a reduction in the aperture efficiency of pixels for the application of the transistor to a switching transistor of a liquid crystal device. These deficiencies are addressed by the present invention.